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Op Amp Model - Level 3


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Input Offset Voltage and Bias Currents

CIRCUIT
 

                       OP3_VOFF_IB.CIR             Download the SPICE file

Gone forever is the ideal op amp we first encountered in our introductory courses and texts. Just one more departure from the ideal is the behavior of the input stage.

  It does not have zero current into the terminals.
  It does not produce zero volts output with zero volts across the input.

There is some current flowing into the device's input. And, its takes a small voltage at the input to bring the output to zero. These two undesirable facts of life are forewarned in the data sheets as the input bias current and input offset voltage. Ignoring these characteristics can lead to unwanted voltages in your circuit. First we'll develop a SPICE model to include the nature of op amp inputs. Then, we'll point you to a couple of hands-on circuits to help you overcome the op amp's shortcomings.

 

INPUT OFFSET VOLTAGE

You can model the input offset voltage, Voff, by placing a voltage source in series with one of the inputs. Which polarity? The spec sheet typically gives a value like 1mV so just pick one. And then simulate it again with the opposite polarity.

 

INPUT BIAS CURRENTS

A bias current flows into both the positive and negative terminals, Ib+ and Ib-. There's a couple ways to simulate them depending on basic structure of your op amp model.

1) If your model's input stage uses SPICE's ideal controlled sources (VCVS, VCCS, etc.), simply hang a current source, IBPOS and IBNEG, on the input terminals. This method applies to the Basic Op Amp Model.

2) If your input stage is built with transistor devices (BJTs, FETs, etc), then choose the device parameters to get the right amount of current flowing into its input terminals. This simulates more closely the actual innards of an op amp. For example, a BJT biased at Ie = 1 mA, produces the desired Ib via the right choice of the BETA parameter.

Ibias = Ie / Beta

This applies to the  Intermediate Op Amp Model described on this site.

 

INPUT OFFSET CURRENTS

As may be expected, the input bias currents are not matched exactly. The difference is specified as the input offset current, Iboff  =  Ib+ - Ib-. Again, you've got a couple of choices for simulating this effect.

1)  Adjust one or both bias currents up or down to model the difference in bias currents.

2)  Strap a current source equal to Iboff / 2 across the input terminals to achieve the same effect. This current source gives Iboff / 2 to one input while taking away the same amount from the other input creating a difference of Iboff.

Just like the input offset voltage, this error can be either polarity.

 

OP AMP MODEL WITH INPUT ERRORS

Here's our Intermediate Op Amp Model complete with input error sources.

Voltage source VOFF supplies a 1 mV input offset voltage. Q1 and Q2's base current produce a 10 nA input bias currents due to emitter currents Ie = 0.5 mA current and choosing BETA = 50000.

Ib = Ie / BETA
    = 0.5A / 50000
    = 10 nA

Finally, IBOFF = 0.5 nA forces an input offset current of 1.0 nA. The subcircuit for this model is available in the file OPMODEL_VOFF_IB.CIR.

 

HANDS-ON CIRCUITS

Ready to roll up your sleeves and take on the input error sources? There's a couple of SPICE topics that show how these sources can potentially ruin your circuit and what you can do about it. You can find them at Input Offset Voltage and Input Bias Current.

 

SIMULATION NOTES

Take a quick refresher tour of the Intermediate Op Amp Model.
For a description of all op amp models, see Op Amp Models.
For a quick review of subcircuits, check out Why Use Subcircuits?
Get a crash course on SPICE simulation at SPICE Basics.
A handy reference is available at SPICE Command Summary.
This model can be used with many of the op amp circuits available from the Circuit Collection page.

 

SPICE FILES

Download the file or copy this netlist into a text file with the *.cir extension.

OPMODEL3_VOFF_IB.CIR - OPAMP MODEL WITH INPUT OFFSET VOLTAGE AND BIAS CURRENTS
*
* SIGNAL SOURCE
VS	1	0	DC	0V
*
* POWER SUPPLIES
VCC	10	0	DC	+15V
VEE	11	0	DC	-15V
*
R1	0	2	10K
R2	2	3	10K
XOP	1 2 3  10 11	OPAMP2
RL	3	0	100K
*
*
* OPAMP MACRO MODEL (INTERMEDIATE LEVEL)
*
*                IN+ IN- OUT  VCC  VEE
.SUBCKT OPAMP2   1   2   81   101   102
VOFF	1	9	DC	0.001
IBOFF	1	2	DC	0.5E-9
*
Q1	5 9	7	NPN
Q2	6 2	8	NPN
RC1	101	5	95.49
RC2	101	6	95.49
RE1	7	4	43.79
RE2	8	4	43.79
I1	4	102	0.001
*
* OPEN-LOOP GAIN, FIRST POLE AND SLEW RATE
G1	100 10	6 5 0.0104719
RP1	10	100	9.549MEG
CP1	10	100	0.0016667UF
*
*OUTPUT STAGE
EOUT	80 100	10 100	1
RO	80	81	100
*
* INTERNAL REFERENCE
RREF1	101	103	100K
RREF2	103	102	100K
EREF	100 0	103 0 1
R100	100	0	1MEG
*
.model NPN  NPN(BF=50000)
*
.ENDS
*
* ANALYSIS
.TRAN 	0.1MS  10MS
*
* VIEW RESULTS
.PRINT	TRAN 	V(3)
.PROBE
.END

 

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