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Diff Amp with Current Mirror
DIFF_AMP_W_MIRROR.CIR Download the SPICE file
In an audio input differential stage, you often see the simple collector resistor replaced with a current mirror. Why bother? The payoff is two fold. First, you get twice the gain and current output, typically a good thing for an audio amp. And second, the current mirror nicely balances the current between Q1 and Q2, (a feat not so easily accomplished with resistors at the collectors.). What's all the fuss about balance? You'll see below that even a small imbalance can kill your best efforts at low distortion.
We already discovered how the input differential stage works in the basic audio amplifier. The input voltage V(2,3) causes a change in Q1's collector current Ic1 which gets passed on to the next stage. But what about Q2's collector current? In a sense, it gets wasted. Wouldn't it be loverly if Ic2 could be mirrored and summed with Ic1?
The secret of the current mirror is in the set of twin transistors wired back to back.
Notice, how the circuit forces their Vbe's to be equal. Now, having matched characteristics forces both emitter currents Ie to be equal. Starting with Kirchoff's current laws you get some simple equations
Then rearrange each equation to
Finally, take the ratio of the two equations and simplify to get
Beastly! The gain from input to output is approximately unity. For a reasonable beta (>100), the mirrored current should be within a few percent of the input!
TWICE THE JUICE
Let's put the current mirror to good use. Q8 and Q9 take the once wasted Ic2, mirror it and sum it with Ic1. In the previous design, the diff amp with resistor load produced an output ic1 = vin·1/2·gm1 where vin = V(2) - V(3). But, with the help of the twins (Q8,Q9), the total output current fed to the next stage becomes
You've just doubled your open-loop gain. This also doubles the current output to next stage allowing twice the slew rate for a given compensation cap CC. Life is good.
To test the circuit, we've added a transimpedance amplifier. This op amp based stage converts the current output of the diff amp into a voltage. It provides a low impedance input that is biased one diode drop above the negative rail. Resistor RF1creates a handy place to measure the output current from the differential amplifier.
VS1 generates an 10 mVpeak 1kHz sinewave input signal. VBIAS1 generates a DC offset (initially 0V) used later to deliberately imbalance the currents through Q1 and Q2. Why? We can then see below - via Fourier Analysis - its horrible effects on distortion.
CIRCUIT INSIGHT Run a Transient Analysis on the SPICE file DIFF_AMP_W_MIRROR.CIR. Plot the collector currents IC(Q1) and IC(Q2). Note, they're both biased at 500 uA and swing about 100 uA peak in opposite polarities. Without the current mirror, only one of these collector currents gets fed to the next stage. With the current mirror, checkout the total current delivered to the next stage by plotting I(RF1). You should see 2x the peak current. Why? Q9 and Q8 duplicate and invert Ic2 over to the Q1's collector where Itot = Ic1-Ic2. When VS1=0, the currents cancel and you get Itot = 0. When VS1 causes Ic1 and Ic2 to swing in opposite polarities, then Itot = 2 x Ic. Now you get twice the transconductance compared to the single ended diff amp.
CURRENT MIRROR GAIN
How well does Q8 and Q9 mirror Q2's collector current? First, let's see what the theory predicts. With β=100 we should expect Io / Iin = 1 / ( 1 + 2/β) = 0.98. So, we should see 98% of Ic2 mirrored over to Q1's side.
CIRCUIT INSIGHT Run a Transient Analysis and plot IC(Q2) and -IC(Q8). At t=0, read the Ic2 and -Ic8. Use a calculator to determine the ratio. Does the current gain come close to 0.98 as calculated?
BALANCE AND DISTORTION
How important is a balanced diff amp to low distortion design? Let's measure the distortion using the Fourier Analysis in SPICE. The following statement
calculates the Total Harmonic Distortion (THD) at node 7 assuming 1 kHz as the fundamental frequency. Set VS1 to a 10 mVpeak, 1 kHz sinewave. Set the offset VBIAS1 = 0V.
CIRCUIT INSIGHT Run a Transient Analysis and plot IC(Q2) and IC(Q1). At t=0, read the Ic1 and Ic2. They should be balanced nicely. To check the THD, open the SPICE output file (*.out). This is a text file showing the SPICE results. Near the end of the *.out file should be the Fourier Analysis displaying the THD. With VS1=10 mVpeak and VBIAS = 0V, you should read a distortion of less than 1%.
But suppose our transistors Q1 and Q2 are not perfectly matched. Set VBIAS=0.002 to simulate a 2mV offset. Rerun the simulation. What happened to the balance between Ic1 and Ic2 at t=0? Worse yet, what happened to the THD? Yes indeed, an imbalance of only several percent between Ic1 and Ic2 has a significant impact on THD! Keep increasing VBIAS1. How bad does the distortion become? Set VBIAS1 back to 0V; then begin increasing VS1. How big can VS1 get before THD grows out of hand?
RC1 vs. CURRENT MIRROR
Now imagine you didn't have the current mirror, just a single resistor RC1 at Q1's collector. How well are the Ic1 and Ic2 balanced? Good question. That requires tweaking of RC1 depending on the desired Ic1 and Vbe of the next stage. Problem: Vbe is temperature dependent! And if you decide to change the first stage bias (Ic1 and Ic2), you've got to tweak RC1 all over again. The final nail in the RC1 coffin is that the amplifier gain is only half current-mirrored output.
Download the file or copy this netlist into a text file with the *.cir extension.
DIFF_AMP_W_MIRROR.CIR - DIFFERENTIAL AMP WITH CURRENT MIRROR * POWER SUPPLIES VCC 100 0 DC +15V VEE 101 0 DC -15V * * INPUT VOLTAGE VS1 2 0 AC 1 SIN(0 0.01V 1KHZ) VBIAS1 3 0 DC 0.00V * * DIFF AMP RE1 100 8 14.3K Q1 4 2 8 QPNP Q2 5 3 8 QPNP * CURRENT MIRROR Q8 4 5 101 QNPN Q9 5 5 101 QNPN * * TRANSIMPEDANCE AMP R10 100 6 10K D10 6 101 D1N4148 RF1 4 7 1K EOPAMP1 7 0 4 6 1000000 * * * DEVICES .model QNPN NPN(BF=100) .model QPNP PNP(BF=100) .model D1N4148 D(Is=0.1p Rs=16 CJO=2p Tt=12n Bv=100 Ibv=0.1p) * CHECK DISTORTION WITH FOURIER SERIES ANALYSIS .FOUR 1KHZ V(7) * .TRAN 50US 1MS .PROBE .END
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