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Download SPICE Netlist or LTSPICE
Schematic
Right Click on filename, select "Save link as..."
Let's build an ultra-lite SMU to learn digital control. Why? A small system provides an easy on-ramp to grasp bigger
ideas without getting lost in a myriad of circuit details. First,
we'll focus on the essential DNA of a digital SMU. From there, you can
develop more complex SMU's on a solid foundation.
You'll get a hands-on SPICE simulation and Excel Design File. Coming soon - we'll build a prototype with the Arduino and a just few components.
SMU Specifications
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What are the basic blocks of a digital SMU? Both analog and digital SMU's carry similar functions. However, digital SMU's import many key functions into the Software. What's the advantage? Software not only reduces the amount of hardware, but offers flexibility in functions, gains and settings.
Get a review of the basic blocks.
Many SMU functions have been pulled into the Software (Set Point, Error Calc, Controller). The most challenging block is the Digital Controller or Integrator (see below.)
The Hardware provides the interface to the real world through Analog / Digital Converters (DAC, ADCs). Both the DAC and ADC's have analog operating ranges of 0 to 5V.
The current sense resistor (Rs = 100ohms) consumes 0.5V max of the 5V range. This leaves 4V for the actual voltage range and the remaining 0.5V for design margin.
Lastly, the reason for the SMU is the Device Under Test (DUT), in this case a resistor Rdut.
The integrator keeps a running sum of the error signal.
What happens when the feedback reaches the set point? The error goes to zero and the integrator output holds steady.
How can we transform an analog integrator into a digital version in software? You can think of the software as calculating the integrator's output at every sampling interval Ts. A little theory can bridge the analog and digital domains.
While more complex digital models of the integrator exist, this simple version builds a basic understanding and intuition of this key block.
Here's one SPICE implementation that captures the Software's function of the digital integrator.
The circuit should calculate the running sum of error using current (n) and previous (n-1) values. (See section above.)
int(n) = int(n-1) + Ki * error
In SPICE, the source E_INT calculates this as
V = v(int1) + Ki * v(error)
Capacitors CR0 and CR1 act as "storage registers" for the current sum (int0) and previous sum (int1).
Other SPICE models are possible - some implementations use transmission line delays as storage elements.
How can we create a SPICE circuit to mimic the software functions?
While just an approximation, a SPICE circuit can capture the spirit of the
software functions. Many simulation possibilities exist! Here's one implementation
to build some hands-on understanding and intuition.
SOFTWARE
ANALOG / DIGITAL INTERFACE
CURRENT SENSE AND DUT
Explore the hands-on spreadsheet with the circuit calculations!
Let's see the Digital SMU circuit in action. For FV or FI mode, just enable / comment the relevant .PARAM statements:
FV MODE Enable the .PARAMs for FV mode and run a TRAN simulation of SMU-FVFI-ciruit-1.cir (or *.asc). Add traces v(set) and v(feedback). Does v(feedback) rise to the set point v(set)?
Check out how the output (feedback) stair steps every Ts interval toward the desired value. Add a plot, then add traces v(error) and v(int0). Notice the operation of the digital integrator (int = int1 + Ki*error): as the error gets smaller, the increments of the running sum get smaller (int0).
Let's see how speed control works! Adjust Kint up by 2x or 3x and rerun the simulation. Does the output rise faster or slower?
FI MODE Enable the .PARAMs for FI mode and run a TRAN simulation. Does the v(feedback) rise to the desired set point v(set)?
Adjust Kint up by 2x or 3x and rerun the simulation. Does the output rise faster or slower?
Download SPICE Netlist or LTSPICE
Schematic
Right Click on filename, select "Save link as..."
* SMU-1-FVFI-basic-digital-1.cir
*
* FV Mode Params
.param fmode=0V set=5.0V Rs=1k Rdut=20k Kint=10000
* FI Mode Params
* .param fmode=5V set=0.005A Rs=100 Rdut=50 Kint=20000
*
* Digital Control Params
.param Ts=10us Ki=Kint*Ts
*
* Set Point
Vs set 0 PWL(0us 0 1us {set})
*
* Error
E_ERR error 0 set feedback 1.0
*
* Digital Controller
* Integrator
E_INT int 0 VALUE = { v(int1) + Ki*v(error) }
* Store int(n)
SR0 int0 int clk0 0 SW1
CR0 int0 0 100pF
*
E_INT0 vctl 0 int0 0 1
* Store int(n-1)
SR1 int1 vctl clk1 0 SW1
CR1 int1 0 100pF
*
* DAC Output
E_DAC V_a 0 vctl 0 1
*
* Current Sense
Rs V_o V_a {Rs}
*
* Device Under Test (DUT)
Rdut V_o 0 {Rdut}
*
* Va ADC
E_ADC1 Va 0 V_a 0 1
*
* Vo ADC
E_ADC0 MV 0 V_o 0 1
*
* Current Calc
E_MI MI 0 Va MV {1/Rs}
*
* FMODE select
Vmode1 fmode 0 {fmode}
S1a MV feedback fmode 0 SW2
S1b MI feedback fmode 0 SW1
*
* Sampling Clocks
VCLK0 clk0 0 PULSE(0V 5V 0us 0.05us 0.05us 0.25us 10us) AC 0V
VCLK1 clk1 0 PULSE(0V 5V 5us 0.05us 0.05us 0.25us 10us) AC 0V
*
* Simulation
.tran 1.2ms
*
* Switch Models
.model SW2 SW(Ron=1 Roff=1e12 Von=0V Voff=5V )
.model SW1 SW(Ron=1 Roff=1e12 Von=5V Voff=0V )
.end
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