SPICE Model: Opamp_3

SCHEMATIC

 

• Behaviors Modelled
  • opamp_1
    • Gain
    • Bandwidth
    • Input / Output Resistance
  • opamp_2
    •  add  Max Slew Rate
  • opamp_3
    • add  Voltage / Current Limits, Floating Vref

• LTSPICE files
  • Op Amp Schematic: Opamp_3.asc
  • Op Amp Symbol: Opamp_3.asy
  • Test Schematic: Test_Circuit_opamp_3.asc
  • Right Click on filename, select "Save link as...",

• Design Guide
  • After verifying a circuit topology, set voltage and current limits to those expected in op amps available in your company stock.

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INPUT PARAMETERS

• Aol - Open-Loop DC Gain
• fu - Unity-Gain Frequency.
  •  Also called Gain-Bandwidth-Product (GBP) in most op amps.
• Slew - Maximum rate of voltage change dV/dt achievable by the device.
• Ro - Output Resistance.
• vlim - The maximim voltage the output can swing to within the supply rails.
• ilim - The maximum output current possible into a short circuit.

HOW IT WORKS

• DC Gain provided by current source B_G1 (gain of gm) and R1
  • v(out) = i(B_G1)*R1 = (v(+) - v(-))*gm*R1
  • Aol = gm*R1
• Slew Rate defined by max B_G1 max current flowing into C1.
  • B_G1 current is bounded using LIMIT function defined by I1max
  • I = limit( {gm}*(v(+) - v(-)), +I1max, -I1max )
  • Slew Rate = dV/dt = I1max / C1
• 1st Pole formed by R1, C1
  • fp1 = 1/(2*pi*R1*C1)
• Unity-Gain Frequency defined by DC Gain and 1st pole
  • fu = Aol*fp1
• The Voltage Max is limited by Diode / Voltage pairs DVLIM_P / VLP and DVLIM_N / VL_N.
  • Normal mode: Diode / Voltage pairs are effectively out of the circuit.
  • Limit mode:
    • If v_g1 > (vcc - VL_P), then DVLIM_P conducts and clamps to vg1 ≈ vcc - VL_P.
    • If v_g1 < (vee + VL_N), then DVLIM_N conducts and clamps to vg1 ≈ vee - VL_N.
  • Note: diodes are near ideal.
    • .model DVLIM D( Vfwd=0V Ron=0.1 )
• The Max Output Current into a short circuit is achieved using diodes VILIM_P and VILIM_N
  • LTSPICE provides a handy diode parameter Ilimit.
    • .model DILIM D( Ron=0.1 Vfwd=0V Ilimit={Ilim} )
• The internal voltages ride on a reference voltage v(vmid), set midway between the supply rails by RM1, RM2 and Emid.
  • 
    
  • This avoids simulation errors when both op amp rails are floated on a higher voltage.

INTERNAL CALCULATIONS

• .param I1max = 0.001   (choose G1's max current).
• .param C = I1max / (slew * 1e6)
• .param fp = fu/Aol
• .param C = 1/(2*pi*fp*R)
• .param gm = Aol/R
• .param vlim_p = vlim + I1max*Ron
• .param vlim_n = vlim + I1max*Ron

TEST IT

• Run a .TRAN simulation of Test_Circuit_opamp_3.asc
• Circuit: R1=10k, R2=40k, Rload=10k and Vstep=2V.
• Supplies: vcc=12V, vee=-12V
• V Limit Test
  • Set Rload=10k, vlim=2.5, ilim=0.035
  • Run a sim and plot v(vs) and v(vo).
  • Does the output reach expected 2V * 5V/V = 10V?
  • Change limit to vlim=1.5 and retest.
  • Does vo reach 10V?
• I Limit Test
  • Set Rload=200
  • Run a sim and plot v(vs) and v(vo).
  • Does the output reach expected 2V * 5V/V = 10V?
  • Plot i(Rload) - limited to 35mA?
  • Set ilim=0.055 and retest.
  • Does vo reach 10V (50mA)?

 

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