Ro and Cload

CIRCUIT

Schematic: Op_Amp_Cload.asc
Sch Open Loop: Op_Amp_Cload - OL.asc
Op Amp Symbol: Opamp_2.asy
Op Amp Shematic: Opamp_2.asc
Right Click on filename, select "Save link as...",

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SPEC IT

Intro	One of the big challenges in analog design is driving a capacitive load! You may need to   • drive a coax cable.   • buffer an ADC's ref pin having a huge bypass cap. So, what's the big deal? Cload (and Ro) form a low-pass filter which can lead to ringing and oscillations!
Definitions	Ro - the output resistance of the op amp (typically 20 to 50 ohms.) Cload - the cap load at the op amp's output (typically 10s of pF to 10s of uF).
Design Goal	A stable amplifier output (minimial overshoot and ringing).
Design Spec	Overshoot < 10% given Ro = 50 ohms, Cload = 22nF and 0.1V step voltage input.

DESIGN IT

• Circuit Design
  •  Kcl = (R2+R1)/R1 = 1V/V
  • Choose: R1=10k
  • Calc: R2=Open (1e9)
• Op Model Param
  • Aol=100000 fu=10e6 slew=10 Ro=50
  • Cload = 22nF
  • Riso = 0.1 (Isolation Resistor, unused for now).
• Circuit Test
  • Input:  Vs = 0.1V voltage step
  • Output:  Vo = 0.1V
  • Expected Overshoot < 10% or Vo < 0.11V max.

TEST IT

• Run a Transient simulation. (.TRAN)
• Plot the output v(vo)
• Did it meet spec?
  • If vo < 0.11V, then PASS, else FAIL
•  DESIGN ISSUE: The output fails to meet the overshoot design spec! 

SOLVE IT

• Incrementally increase Riso to 2, 4, and so on.
• Rerun the SPICE simulation after each increment.
• What value of Riso is required to acheive the <10% design spec?

THEORY REFRESH

• How does Cload cause instability?
  • HEAD'S UP: Took me several passes through this type of design adventure to wrap my understanding and skills around it.
• For better insight, check out the circuit showing the internal Ro.

 

• Theory Refresher - 1
• WITHOUT Riso
• Notice how Ro and Cload form a Pole (low-pass filter) at
      fp = 1/(2*pi*Ro*Cload).
• Yikes! LP filters cause Time Delays (negative Phase shifts).
• Delays cause ringing and oscillations inside of feedback loops!
• WITH Riso
  • Adding Riso creates a Pole AND a Zero
  • The low-pass pole adds NEG phase (bad!)
       fp = 1/(2*pi*(Ro+Riso)*Cload)
  • The high-pass zero adds POS phase (good!)
       fz = 1/(2*pi*Riso*Cload)
  • Design Goal
       Increase Riso until fz approaches fp enough to reduce overall neg phase shift.

 

• Theory Refresher - 2 (more intuitive)
• You could say at f>>1 Riso isolates Ro from Cload's reactance. How?
• Resistor Riso adds a Real part to Cload's Reactance.
  
• As f increases, Xc decreases and Zload looks more resistive (like Riso)
  • output network behaves less like a low-pass filter
  • adds less neg phase shift with Ro.

 

• Open-Loop Analysis - Let's break out the design power tool that can reveal problems and help find solutions. Here's one approach

• Open-Loop Analysis in a nutshell.
  • Set the signal source Vs = 0V.
  • Break the loop open between R1,R2 divider and op amp's neg input.
  • Insert Vtest into the opened loop.
       Important impedance condition around Vtest:  Z+ >> Z-
  • Run an AC analysis and plot the Magnitude and Phase around the Open Loop, v(vfb)/v(vtest).
  • Check the Phase shift (time delay) where the Magnitide crosses 1V/V (or 0dB)
    

• Design Goal:  Move the total Phase at 0dB more positively away from -360 (or +0) deg for less overshoot and ringing.

Step Response	Phase (deg)
Oscillations - UNSTABLE	-360 (or 0)
40% Overshoot	-330 (or +30)
25% Overshoot	-315 (or +45)
10% Overshoot	-300 (or +60)
No Overshoot - Optimal Response	-270 (or +90)

• So what happened to our original design?
  • Let's calc the pole frequency of Ro, Cload.
        fp = 1/(2*pi*Ro*Cload)
            = 1/(2*pi*50*22nF) = 144kHz.
  • Bad news! The pole fp (neg phase) occurs well below the op amp's fu = 10MHz (likely causing instability.)
• Adjust Riso with Open-Loop Analysis
  • SPICE file:  op_amp_cload - OL.asc
  • NO Cap Load:  Run the AC sim with Cload=0nF, Ro=50, Riso=0.1, Cload=0nF and plot v(vfb)/v(vtest).
    • The Phase at 0dB (1V/V) should be close to -270 deg (or +90 deg), very Stable.
  • With Cap Load: Run the sim with Cload=22nF and plot v(vfb)/v(vtest).
    • The Phase at 0dB should be close to -360 deg (or 0 deg) at 0dB, very Unstable.
  • Adjust Riso: Increase Riso from 0.1 to 4 or 6 and rerun the sim.
    • The Phase at 0dB should have moved to a stabler range away from -360 (or 0) deg.
• Choose a final value for Riso and retest the closed loop circuit op_amp_cload.asc. Did your circuit meet overshoot spec?

 

Final Note: Riso might cause an unacceptable voltage drop if the load draws significant current. In that case, check out driving a cap load with a feedback point at the capacitor.

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