Error Budget Analysis

Part 1 - Offset Errors

INTRO

You've designed the circuit and chosen components. But before you start to build anything, a critical question arises: 

  Can you verify that the circuit will meet its accuracy spec?

An Error Budget Analysis (EBA) is one of the coolest and most challenging analysis you'll perform. Also called a Tolerancw Stackup Analysis, the method evaluates how each Error Source impacts the circuit's Offset or Gain Errors.

Lastly the errors are summed and checked if they fly under the allowed Error Budget (Requiements). If YES, then high fives! if NO, then it's time to investigate better components or a better suited circuit topology.

In Part 1 you'll learn to analyze the Offset Errors; Part 2 the Gain Errors.

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OFFSET AND GAIN ERRORS

• Ideal Amplifier with Gain K
  • Vo = Vin*K
• Actual Amplifier with errors
  •  Vo = Vin* (K+∆K) + ∆Voffset
•  ∆K  - Gain Error
  • change in Gain from ideal (K).
  • also called Slope, Span error
•  ∆Voffset  - Offset Error
  • change in offset from ideal (0V)
  • also called Intercept, Zero Error
• Combined error
  • Error = ±∆Voffset  + ( ±∆K x Reading )

 

MAX BUDGET

• Max allowable error from requirements.
  • 4V:    ∆Voffset = 15mV,   ∆K = 1.5% of Reading
  • 20V:  ∆Voffset = 75mV,   ∆K = 1.5% of Reading

 

CIRCUIT WITH ERRORS

Here's a view of the instrument's Offset and Gain errors. We'll meed to find the errors for both the 4V and 20V Ranges.

ATTENUATOR GAINS

• 4V: SW1 On, SW2 Off
    Kdiv = 1.0
• 20V: SW1 Off, SW2 On
    Kdiv = R2/(R1+R2)
           =200k/(800k+200k)
           = 0.2

ERROR SOURCES

Offset Errors	Value
ADC Offset (Zero) Error	2 LSBs
ADC Resolution Error	1/2 LSBs
SW1 Off-State Leakage Current	1nA
SW2 Off-State Leakage Current	1nA

Gain Errors	Value
R1 Tolerance	1%
R2 Tolerance	1%
ADC Gain (Span) Error	2 LSBs
Voltage Reference Error	50mV

 

ADC OFFSET ERROR

We'll walk through the method with this relatively straightforward error!

• Identify Error Source
  •  Voff = 2 LSBs x 2^N / Vrefin
            = 2 x 1024 / 5V
            = 10mV
• Choose Analysis Node - a convenient location to
  calculate the error's impact on the circuit.
  • vadc1
• Calculate Sensitivty - how does error impact Analysis Node?
  • S = vadc1 / voff = 1
    (see Sensitivty Calc below)
• Calculate Error
  • ∆Voffset = voff x S
               = 10mV x 1
               = 10mV
• Calc Gain from Input Vin to Analysis Node
  • Ka_4V = vadc1 / vin = Kdiv_4V = 1.0
  • Ka_20V = vadc1 / vin = Kdiv_20V = 0.2
• Calc Error Referred to Input (RTI)
  • 4V: ∆Voffset_RTI = ∆Voffset / Ka_4V
                             = 10mV / 1.0
                             = 10mV
  • 20V: ∆Voffset_RTI = ∆Voffset / Ka_20V
                             = 10mV / 0.2
                             = 50mV

NOTE! A 10mV ADC error produces a 50mV equivalent error at the input on the 20V Range.

  

ADC RESOLUTION ERROR

The intrinsic error of an ideal ADC is 1/2 LSB due to quantization error!

• Identify Error Source
  •  Vresf = 1/2 LSBs x 2^N / Vrefin
            = 1/2 x 1024 / 5V
            = 2.5mV
• Choose Analysis Node - a convenient location to
  calculate the error's impact on the circuit.
  • vadc1
• Calculate Sensitivty - how does error impact Analysis Node?
  • S = vadc1 / vres = 1
    (see Sensitivty Calc below)
• Calculate Error
  • ∆Voffset = vres x S
               = 2.5mV x 1
               = 2.5mV
• Calc Gain from Input Vin to Analysis Node
  • Ka_4V = vadc1 / vin = Kdiv_4V = 1.0
  • Ka_20V = vadc1 / vin = Kdiv_20V = 0.2
• Calc Error Referred to Input (RTI)
  • 4V: ∆Voffset_RTI = ∆Voffset / Ka_4V
                             = 2.5mV / 1.0
                             = 2.5mV
  • 20V: ∆Voffset_RTI = ∆Voffset / Ka_20V
                             = 2.5mV / 0.2
                             = 12.5mV

NOTE! A 2.5mV ADC resolution error produces a 12.5mV equivalent error at the input on the 20V Range.

  

SW1 OFF-STATE CURRENT

Although currents are typically relatively small, they can cause significant voltages flowing into relatively large resistors.

• Identify Error Source
  •  Ioff = 1nA
• Choose Analysis Node - a convenient location to
  calculate the error's impact on the circuit.
  • v1
• Calculate Sensitivty - how does error impact Analysis Node?
  • S = v1 / Ioff = 200k || 800k = 160k
    (see Sensitivty Calc below)
• Calculate Error
  • ∆Voffset = Ioff x S
               = 1nA x 160k
               = 0.2mV
• Calc Gain from Input Vin to Analysis Node
  • Ka_4V = v1 / vin = Kdiv_4V = 1.0
  • Ka_20V = v1 / vin = Kdiv_20V = 0.2
• Calc Error Referred to Input (RTI)
  • 4V: ∆Voffset_RTI = ∆Voffset / Ka_4V
                             = 0.16mV / 1.0
                             = 0.16mV
  • 20V: ∆Voffset_RTI = ∆Voffset / Ka_20V
                             = 0.16mV / 0.2
                             = 1.1mV

NOTE! Although Error is insignficant, still need to verify and document.

 

SW2 OFF-STATE CURRENT

Although currents are typically relatively small, they can cause significant voltages flowing into relatively large resistors.

• Identify Error Source
  •  Ioff = 1nA
• Choose Analysis Node - a convenient location to
  calculate the error's impact on the circuit.
  • v1
• Calculate Sensitivty - how does error impact Analysis Node?
  • S = v1 / Ioff = 0
    (see Sensitivty Calc below)
• Calculate Error
  • ∆Voffset = Ioff x S = 0V
• Calc Gain from Input Vin to Analysis Node
  • Ka_4V = v1 / vin = Kdiv_4V = 1.0
  • Ka_20V = v1 / vin = Kdiv_20V = 0.2
• Calc Error Referred to Input (RTI)
  • 4V: ∆Voffset_RTI = ∆Voffset / Ka_4V = 0V
  • 20V: ∆Voffset_RTI = ∆Voffset / Ka_20V = 0V

NOTE! Although Error is zero, still need to verify and document.

 

 

OFFSET SENSITIVITY CALCS

Here's where we do the interesting and sometimes challenging work of finding the Sensitivity.

ADC VOFF, VRES

Find Sensitivity

• Analysis Node: vadc1
• if Vin=0, then voff (or vres) appears at adc1.
• S  = vadc1 / voff = 1
• S  = vadc1 / vres = 1

 

SW1 IOFF

Find Sensitivity

• Analysis Node: v1
• 20V Range: SW1 Off, SW2 On
• To simplify analysis, assume input source resistance Rs and SW2 are essentially short circuits (Rs=0, Ron=0) compared to R1=800k and R2=200k. The circuit reduces to
  .
• S  = v1 / ioff = R1 || R2

 

SW2 IOFF

Find Sensitivity

• Analysis Node: v1
• 4V Range: SW1 On, SW2 Off
• To simplify analysis, assume input source resistance Rs and SW1 are essentially short circuits (Rs=0, Ron=0) compared to R1=800k and R2=200k. Then circuit reduces to
  .
• v1 = 0V (GND), therefore S  = v1 / ioff = 0

 
 

TOTAL OFFSET ERRORS

Worst Case Analysis estimates the total error under the most unfavoable conditions: all errors at their maximum limit AND in the same polaritiy.

• WCA = | ∆Voffset1 | + | ∆Voffset2 | + ...
        = |ADC_voff_RTI| + |ADC_vres_RTI| + |SW1_ioff_RTI| + |SW2_ioff_RTI|
• 4V:  WCA = |10mV | +  | 2.5mV | +  | 0V | + | 0V |
                = 12.5mV
• 20V:  WCA = | 50mV | +  | 12.5mV | +  | 1.1mV |  +  | 0V |
                  =  63.6mV

Does the Total Error fly under the Error Budget (Requirements)?

• 4V:  WCA = 12.5mV < 15mV?
     Yes - PASS! 
• 20V: WCA = 63.6mV < 75mV?
     Yes - PASS! 

Congratulations if you've traveled this far - you deserve a coffee, tea or treat! We've navigated a number of key concepts together that can help build your EE power toolkit.

 

HANDS-ON

Play in the Excel file - modify values, see what happens!

• Excel File:  DVM1_-_EBA_Offset_Gain_Errors1.xlsx
• Right Click on the filename, select "Save link as...".

Input Range

• Suppose you needed to meet a total offset spec of 10mV on the 4V range? What ADC offset error (now voff = 2 LSBs) would be required to meet the new spec?

 

NEXT UP

With the Offset Errors tallied, time to see how the Gain Errors stack up.

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