Stray Capacitance (Cstray)

CIRCUIT

Schematic: Op_Amp_cstray.asc
Open Loop Sch: Op_Amp_cstray - OL.asc
Op Amp Symbol: Opamp_2.asy
Op Amp Shematic: Opamp_2.asc
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SPEC IT

Intro	You can't avoid these unwanted effects in your op amp circuit:  • stray capacitance on PCB traces from R1, R2 junction to the op amp's negative input.  • parasitic capacitance internal to op amp device at input pins. So, how does it effect your design? These capacitances form a low-pass filter which can lead to ringing and oscillations!
Definitions	Cstray - the total capacitance due to PCB traces and active/passive devices on that node. Ccomp - A physical cap added by the designer to compensate for Cstray.
Design Goal	A stable amplifier output (minimial overshoot and ringing).
Design Spec	Overshoot < 10% given Cstray = 10pF and a 0.1V step voltage input.

DESIGN IT

• Circuit Design
  •  Kcl = (R2+R1)/R1 = 3V/V
  • Choose: R1=100k
  • Calc: R2=200k
• Op Model Param
  • Aol=100000 fu=10e6 slew=10 Ro=50
  • Cstray = 10pF
  • Ccomp = 0pF (unused for now).
• Circuit Test
  • Input:  Vs = 0.1V voltage step
  • Output:  Vo = 0.3V
  • Expected Overshoot < 10% or Vo < 0.33V max.

TEST IT

• Run a Transient simulation. (.TRAN)
• Plot the output v(vo)
• Did it meet spec?
  • If vo < 0.33V, then PASS, else FAIL
•  DESIGN ISSUE: The output fails to meet the overshoot design spec! 

SOLVE IT

• Incrementally increase Ccomp from 0 to 2pF, 3pF and so on.
• Rerun the SPICE simulation after each increment.
• What value of Ccomp is required to acheive the <10% design spec?

THEORY REFRESH

• How does Cstray (C1) cause instability?
  
• Ideally, the feedback network R1, R2 should act as a simple resistor divider - NO phase shifts.
  
• Unfortunately, Cstray and R1,R2 create a low-pass filter which cause Time Delays (neg Phase shift) in feedback loops - which in turn cause ringing and oscillations!!

• By adding Ccomp (C2) along with Cstray (C1) we get a new feedback transfer function.
  
• Although B looks a bit messy, we can simplify it by setting the time constants equal.
  
• Cool beans! Now we can factor out and cancel the (1+s Rx Cx) leaving REAL terms only (NO PHASE SHIFTS!)
  
• How do we calc Ccomp (C2) given Cstray (C1) and R1, R2?
  
• So what happened to our original design?
• Open-Loop Analysis - Let's get some insight using this design power tool. Here's one approach

 

• Open-Loop Analysis in a nutshell.
  • Set the signal source Vs = 0V.
  • Break the loop open between R1,R2 divider node and op amp neg input.
  • Insert Vtest into the opened loop.
        Important impedance condition around Vtest:  Z+ >> Z-
  • Run an AC analysis and plot the Magnitude and Phase around the Open Loop, v(vfb)/v(vtest).
  • Check the Phase shift (time delay) where the Magnitide crosses 1V/V (or 0dB)

• Design Goal:  Move Phase at 0dB more positively away from -360 (or +0) deg for less overshoot and ringing.

Step Response	Phase (deg)
Oscillations - UNSTABLE	-360 (or 0)
40% Overshoot	-330 (or +30)
25% Overshoot	-315 (or +45)
10% Overshoot	-300 (or +60)
No Overshoot - Optimal Response	--270 (or +90)

• Adjust Ccomp with Open-Loop Analysis
  • SPICE file:  op_amp_cstray - OL.asc
  • NO Cstray:  Run the AC sim with Cstray = Ccomp = 0pF and plot v(vfb)/v(vtest).
    • The Phase at 0dB (1V/V) should be close to -270 (or +90) deg, very Stable.
  • With Cstray: Run the sim with Cstray = 10pF and plot v(vfb)/v(vtest).
    • The Phase at 0dB should be close to -360 (or 0) deg at 0dB, very Unstable.
  • Add Ccomp = (Cstray*R1)/R2 = 10pF*100k/200k = 5pF and rerun the sim.
    • The Phase at 0dB should have returned to -270 (or +90) deg. optimal response.
• Choose a final value for Ccomp and retest the closed loop circuit op_amp_cstray.asc. Did your circuit meet the overshoot spec?

 

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